Automatic test equipment provides semiconductor device manufacturers the ability to test each and every device fabricated. By testing each device, the manufacturer can sort devices having like speeds, and/or separate failed devices from passing devices. In this manner, the manufacturer is able to confidently put fully functioning devices into the marketplace.
FIG. 1 illustrates a typical semiconductor tester, generally designated 10. The tester includes a controller or computer workstation 12 coupled to a testhead 14. The testhead houses large circuit boards, or channel cards 16 that mount the electronics necessary for interfacing with one or more devices-under-test 18 (DUTs). In some instances, the controller may be integrated within the testhead, such that the entire tester comprises an integrated unit.
Modern testers generally have a “per-pin” architecture. A “pin” is circuitry within the tester that generates or measures one signal for the device under test. A “pin” is sometimes also called a “channel.” In a per-pin architecture, each channel can be separately controlled to generate or measure a different signal. As a result, there are many channels inside one tester. The channels are generally controlled by a pattern generator. The main function of the pattern generator is to send commands to each channel to program it to generate or measure one test signal for each period of tester operation.
Testers typically generate waveforms for application to a device-under-test (DUT) with timing generation circuitry that responds to the commands or test patterns generated by the pattern generator. The output of the timing circuitry feeds a formatter circuit typically in the form of a flip-flop. The formatter responds to the timing signals to produce a pulse waveform having edge transitions corresponding to the timing information. The formatted waveform then feeds a pin electronics circuit that interfaces the tester to the DUT pin.
The pattern generation circuitry, the timing circuitry, and the formatter circuitry are typically digital circuits that operate at voltage levels appropriate for high-speed digital systems. CMOS processes are often used to fabricate integrated circuits employing the timing and pattern generation circuitry. CMOS is desirable due to its low-power and high-performance characteristics. In contrast, the pin electronics, and associated digital-to-analog converters (DACS) typically comprise analog circuits often requiring voltages higher than the breakdown voltages for individual CMOS transistors. Bipolar and SiGe processes are often employed for the high voltage analog circuitry.
Conventional automatic test equipment handles the multi-voltage level issue by often forming the digital circuitry on one chip, and the analog circuitry on a separate chip. While this has worked well in many instances, modern semiconductor devices are increasing in pin count, requiring additional channel resources from the tester to adequately test the devices. Having separate integrated circuits for channel resources running on different voltage levels undesirably leads to larger and/or higher numbers of channel cards. Larger testheads capable of receiving additional channel cards of increasing size are often required to meet the demands for more channels.
The size of a test system is very important to semiconductor manufacturers. Semiconductors are often tested in “clean rooms.” A clean room has expensive filtering systems to keep dust and other impurities from corrupting the semiconductor devices, particularly before they are encased in a package. Each square foot of clean room space is very expensive to build and operate. It is thus highly desirable to limit the size of equipment that is placed in a clean room.
Cost is also an important issue for semiconductor device manufacturers. The cost of the silicon occupied by the circuitry inside an integrated circuit represents a small fraction of the overall cost of the device. Packaging the silicon, building a circuit board to hold the device, building a frame to hold the printed circuit boards all add substantial costs to the finished product. All of these costs increase with the number of integrated circuit chips.
Outside the field of automatic test equipment, it is known that CMOS circuits requiring different voltage levels may be employed on the same integrated circuit (chip) through stacking techniques. As shown in FIG. 2, this simple technique employs a “stacked” number of CMOS gates disposed in series between the source voltage VDD and ground to distribute the voltage difference, thereby minimizing breaches of the breakdown voltage for each transistor.
Although this technique works well for its intended applications, the stacked transistors are typically formed with a thicker oxide on the output gates. This increases the size of the transistor substantially to give it a higher breakdown voltage characteristic. As is well known in the art, larger transistors generally reflect reduced switching speeds. The higher breakdown voltage is often necessary because of the uneven division of the source voltage on the stacked transistors. This unevenness typically occurs because of the common transistor bulk connections at Bp and Bn (in phantom). For applications needing high performance switching speeds, the conventional stacking technique is often unacceptable.
What is needed and as yet unavailable is a channel architecture for automatic test equipment that enables the fabrication of circuits operating at different voltages on a single integrated circuit without performance penalties. The channel architecture described herein satisfies this need.